The present invention relates to operations performed by cache memories in a multiprocessor. More specifically, the operations, referred to generically as housekeeping operations, involve looking for entries stored in the cache which must be operated upon and performing the appropriate operation on those entries.
A simple form of housekeeping is the invalidation process described in U.S. Pat. No. 4,481,573. When one of the processors on a bus writes data to an entry in its cache, the other processors on that bus receive a signal causing them to invalidate that same data if they are storing it. The data is identified by a virtual address sent over the bus.
Another form of housekeeping is a flush, described briefly in Katz, R. H., Eggers, S. J., Wood, D. A., Perkins, C. L. and Sheldon, R. G., "Implementing a Cache Consistency Protocol", Conference Proceedings: The 12th Annual International Symposium on Computer Architecture, IEEE Computer Society Press, Piscataway, N.J. 1985, pp. 276-283 as a step for moving data back to main memory. In the multiprocessor described by Katz et al., one processor's cache may be the owner of a cache entry which has been written by that processor, in which case the cache entry as stored by that cache is written back to memory. Katz et al. also describe operations in which copies of an entry in caches other than the owner are invalidated, as in the invalidation process described above. U.S. Pat. No. 4,264,953 describes a more complex form of housekeeping, called a purge operation, which affects cache entries whose addresses are within a range of addresses. This is used where the corresponding data within that range in main memory has been modified, perhaps with data from another source, such as an I/O device, or by changing from non-shared to shared. As a result, any cache entries within the range will be storing potentially incorrect data. Each cache receives a signal identifying the purge operation and also receives two signals indicating the upper and lower limits of the range of addresses to be purged. The respective processor of the cache sends each cache address in sequence. When a cache contains an entry for an address from the processor and that address is within the range, the cache modifies that entry so that if its address is later sent by the processor, a cache miss will occur, requiring retrieval of the correct data from main memory.
It would be advantageous to have housekeeping techniques which are more efficient and provide a wider variety of operations.